In many circuits, it is necessary to generate a voltage which is greater in magnitude than the supply voltage. For example, EPROMs need a programming voltage (V.sub.pp) of approximately twelve voltages. This voltage must normally be generated from a five volt supply coupled to the EPROM circuit. Similarly, EEPROMs require a V.sub.pp of approximately sixteen to seventeen volts which must be generated from the five volt supply voltage. In other instances, a negative voltage must be generated from a negative supply voltage of lesser magnitude or from the five volt supply.
EPROMs and EEPROMs are discussed in greater detail in connection with U.S. Pat. No. 4,569,117, to Baglee et al, issued Feb. 11, 1986, entitled "Method of Making Integrated Circuit With Reduced Narrow-Width Effect", U. S. Pat. No. 4,695,979, to Tuvell et al., issued Sep. 22, 1987, entitled "Modified Four Transistor EEPROM Cell", U.S. Pat. No. 4,669,177, to D'Arrigo et al., issued Jun. 2, 1987, entitled "Process for Making a Lateral Bipolar Transistor in a Standard CSAG Process", U. S. Pat. No. 4,715,014, to Tuvell et al., issued Dec. 22, 1987, entitled "Modified Three Transistor EEPROM Cell", U. S. Pat. No. 4,718,041, to Baglee et al., issued Jan. 5, 1988, entitled "EEPROM Memory Having Extended Life", U.S. Pat. No. 4,736,342, to Imondi et al., issued Apr. 5, 1988, entitled "Method of Forming a Field Plate In a High Voltage Array", U. S. Pat. No. 4,742,492, to Smayling et al., issued May 3, 1988, entitled "EEPROM Memory Cell Having Improved Breakdown Characteristics and Driving Circuitry Therefor", U. S. Pat. No. 4,797,372, to Verret et al., issued Jan. 10, 1989, entitled "Method of Making a Merge Bipolar and complementary Metal Oxide Semiconductor Transistor Device", U. S. Pat. No. 4,804,637, to Smayling et al., issued Feb. 14, 1989, entitled "EEPROM Memory Cell and Driving Circuitry", and U. S. Pat. No. 4,912,676, to Paterson et al., issued Mar. 27, 1990, entitled "Erasable Programmable Memory" all of which are incorporated by reference herein.
Typically, charge pumps are used to generate a voltage of increased magnitude. Present-day charge pumps comprise a series of stages, each stage including a capacitor and an MOS or junction diode. Each stage of the charge pump boosts the magnitude of the voltage signal by a voltage equal approximately to the voltage swing of a clock signal applied to the capacitor less the threshold voltage of the diode.
Typically, the clock signals vary between zero and five voltages. For an MOS diode, the voltage drop is approximately two to three volts, resulting in a voltage boost of approximately two to three volts per stage. A junction diode has a voltage drop of approximately 0.7 volts, resulting in a boost of approximately 4.3 volts per stage. Junction diode charge pumps are difficult to fabricate, however, since the n-well must remain positive with respect to the substrate. If the n-well becomes negative, a substrate diode will result.
The need to increase the density of integrated circuits dictates that the size of each subcircuit be minimized. By reducing the number of stages, i.e., by increasing the voltage boost of each stage, the size of the charge pump can be reduced.
Therefore, a need has arisen for a charge pump with a minimum area requirement.